Language Breakdown
Lines of code distribution across 3 owned repositories
230K
Total LOC
Python
218,208 lines
94.7%
N/A
Tcl
10,970 lines
4.8%
N/A
Verilog
625 lines
0.3%
N/A
SystemVerilog
584 lines
0.3%
N/A
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Python
Tcl
Verilog
SystemVerilog
Collaboration Network
Global Impact visualization
Repos
5
PRs
0
Growth
+18%
Top Collaborators
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Coding Streak
Contribution activity over the past year
1 day
75
Contributions
68
Commits
5
Pull Requests
Jun
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Based on GitHub activity
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Following
5 total
Matt Pocock
@mattpocock
Maxim Brashenko
@j2h4u
Daniel Cela
@CelaDaniel
Claude
@claude
jayanthmb14
@jayanthmb14
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Python
AlgoFPGA
A Xilinx Vivado–based FPGA accelerator library. This repository contains HDL sources, constraint files, and TCL scripts for building and customizing hardware algorithm accelerators. Vivado-generated build artifacts, logs, and temporary files are excluded via .gitignore to keep the repository lightweight, reproducible, and collaboration-friendly.
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Tcl
Aaditya2605
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Open Source Impact
Contributions to external projects
5 merged PRs
Contributed to 2 repositories